FIG. 1 shows a prior-art method for testing and constructing dynamic RAM memories. After fabricating the wafers and before cutting them into individual chips the prior art conducts comprehensive wafer probe tests on the entire wafer. One such test is a D.C. fail test. This test measures the power supply current drawn by each die in active mode and standby mode. If a die draws too much current in either mode, the tester discards the die because the tester assumes the die has a short. Other wafer probe tests conducted on the individual cells, address decoders, and sense amplifiers determine their functionality.
After completion of the wafer probe tests, a laser repair procedure replaces defective memory cells with redundant rows and columns. If the number or placement of redundant rows and columns is not sufficient to repair the defective memory cells, the die is discarded. After completion of laser repair, the prior art retests the wafer. All failing die must be discarded because the prior-art procedures have no way to repair them.
After completing tests on the wafer, the wafer is diced into separate chips and assembled into separate packages. These packaged chips are tested for defects and then endure burn-in tests lasting approximately two days at elevated temperatures of 125.degree. C. After passing the burn-in test, the devices encounter the manufacturer's final tests. These time-consuming, expensive tests include a pattern disturb test and write recovery test in addition to other tests. The chip manufacturer ships passing devices to customers who typically conduct the incoming screening tests on a sample of the devices. After installing these devices into memory systems, the customer tests the memory systems. These tests typically include a second burn-in test.
The testing and manufacturing procedures of the prior art have numerous disadvantages. Prior-art procedures use expensive equipment. The prior art handles the chips extensively and exposes them to electrostatic discharge and other hostile conditions that cause failures. Additionally, prior-art procedures inefficiently test for pattern sensitive defects. Pattern sensitive defects are memory defects that cause failures when the bits have a particular configuration. The prior art conducts tests for these pattern sensitive defects by storing every possible combination of ones and zeros into the memory. Obviously, this procedure is very time consuming if not impossible. Therefore, prior-art procedures miss some pattern sensitive defects. These undetected defects will cause system failures when they occur during field use.
Another disadvantage of prior-art testing and manufacturing procedures is the limited repair capability. The laser repair procedure of the prior art can only repair a small number of cell, column, or row defects. Additionally, the prior-art procedure can not repair defects found after the completion of the laser repair. Since the prior art conducts extensive tests after completing the laser repair procedure, this limitation is particularly troublesome.
The disadvantages discussed above increase the cost of manufacturing memory and decrease the yield of usable memory. Additionally, the disadvantages result in costly system failures. The methods and apparatus in accordance with the present invention obviate these problems.